The present application relates generally to semiconductor device processing, and more specifically to conformal thin film architectures and their methods of production.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. As contact dimensions decrease, however, there is a corresponding increase in contact resistance that poses a challenge to device development.
Merging fins (i.e., at respective source and drain regions) enables partial strapping of the contact plugs, which provides reduced contact resistance without excessively increasing parasitic capacitance. However, due to the narrow dimensions of the device, it is difficult to merge fins without consuming the silicon reservoir of the fins themselves. Moreover, achieving conformal coverage of deposited layers over three-dimensional structures is important in engineering robust device designs having enhanced performance.
In view of the foregoing, it would be advantageous to develop a deposition method to provide controlled conformality of deposited layers, which may additionally be used to enhance or suppress the merging of adjacent structures.